Fabrication of Double Gate FET and Analytical Modeling for Surface Potential and Short Channel Effects

Abstract

This paper explores the solution of surface potential variations for junction less (JL) double gate FET. This was only possible for SOI FET. Drain current and gate to source voltage Vgs characteristics within drain induced barrier lowering (DIBL) and Sub threshold calculations are done using Silvaco TCAD software. Basically In this paper 80nm device is fabricated and then some results are compare with device of 10nm.This is predominantly accurate for technical considerations of awareness where testified doping densities surpass 10 cm2for 11nm to 21nm channel thickness.