Improving Memory Performance Using Cache Optimizations in Chip Multiprocessors

Abstract

The processor-memory bandwidth in current generation processors is the main bottleneck due to a number of processor cores sharing it through the same bus/ processor-memory interface. As a result, the on-chip memory hierarchy in multi core processors has assumed the role of one of the most important resources that should be managed efficiently to alleviate the above problem. Effective utilization of this resource is therefore an important aspect of memory hierarchy design of multi core processors. This is currently an important area of research with a large number of research publications that have proposed a number of techniques to solve the problem. These include novel techniques that were not used earlier either in single core processors or the conventional multiprocessors. This paper presents a survey of all such techniques proposed in recent publications. The major contribution of this paper is the assessment of effectiveness of some of the techniques that were implemented in recent chip multiprocessors. Cache optimization techniques that were identified for single core processors but have not been implemented in multi core processors are also examined to predict their effectiveness.