Control of voltage stress, conduction loss and switching losses through comparison between Hardware design and Simulation of 9 level and 13 level Inverter in APOD strategy


Power electronics devices such as inverters has been get too much importance because of their numerous advantages like change in voltage, harmonic distortion, switching loss and efficiency. When converting DC to AC, we want to achieve required voltage and frequency. While converting DC to AC we generate our required output voltages and frequency but  it causes harmonic distortion. This harmonic distortion can be reduced by introducing multilevel output, which reduces change in voltage, and increase efficiency by staircase voltage levels. Two level inverter can produce only  0 level and any other voltage level but two level inverter is not suitable for higher frequency and higher voltage applications. Output voltage of inverter should be pure sinusoidal waveform without harmonics but practically sine wave has harmonics. In hardware design parallel DC source, bidirectional switches, and large capacitance values are used in order to increase performance efficiency and reduces harmonics. In this paper Nine level and thirteen level inverter efficiency is improved on hardware by applying optocoupler and capacitor techniques with higher input voltage and higher load applications, then hardware results are compared with simulation results.  Capacitors are used before optocouplers which isolates input from output and gets signal from Arduino which is applied at MOSFETS. Control circuit requires high frequency  switches and polarity circuit requires low frequency switches. By lower number of MOSFET,s arrangement the power loss, conduction loss is decreased because when switch components are increased then switching loss and conduction loss increases. The alternative phase opposition deposition (APOD) strategy is selected for comparison. A multicarrier pulse wave modulated (MCPWM) level shifted scheme is used to  control operation of power switches MOSFETS for multilevellevel cascaded multilevel H-bridge inverter CHMLI topology. The results of hardware and simulation are compared in term of improved efficiency, decreased switching and conduction loss,  and lesser voltage stress . The results have high power quality and better reduced electromagnetic interference.

Author Biography

Muhammad Ali Raza, University of engineering and technology lahore

I am Muhammad Ali Raza.I am lecturer in Electrical Engineering department in University of Engineering and technology Lahore. I have done master in engineering from china. My research field is in electronics and communication.

How to Cite
Raza, M. A. (2021). Control of voltage stress, conduction loss and switching losses through comparison between Hardware design and Simulation of 9 level and 13 level Inverter in APOD strategy. University of Sindh Journal of Information and Communication Technology , 5(2), 69-75. Retrieved from

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